A related-art semiconductor apparatus having an electrode pad is generally provided with no device directly under the electrode pad. In this discussion, an electrode pad is defined as an air-exposed region of a metal-wiring layer through a pad opening formed in an insulation film provided on the metal-wiring layer. The electrode pad generally aims to contact a bonding wire or a soldered bump to electrically connect a semiconductor apparatus to an external device, or a test probe to perform a test of the semiconductor apparatus.
One exemplary related-art semiconductor apparatus is illustrated in FIGS. 1A and 1B. FIG. 1A is a top view of the semiconductor apparatus and FIG. 1B is a cross-sectional side view taken in an A-A line of FIG. 1A.
As illustrated in FIGS. 1A and 1B, an interlayer insulation film 13 is formed on a semiconductor substrate 1, and a metal-wiring layer 17 of a metal material is created on the interlayer insulation film 13. Further, surfaces of the interlayer insulation film 13 and the metal-wiring layer 17 are covered by a final protection film 19. The final protection film 19 is provided with a pad opening 21 above a formation area of an electrode pad 23 in the metal-wiring layer 17. A tip of a bonding wire or a soldered bump is connected to the electrode pad 23 through the pad opening 21.
A semiconductor apparatus having more than one metal-wiring layer can also be provided with an electrode pad. For example, FIGS. 2A-2C illustrate cross sections of different related-art semiconductor apparatuses each having a four-metal-wiring-layer structure.
In FIG. 2A, reference numerals 17-1, 17-2, 17-3, and 17-4 denote first, second, third, and fourth metal-wiring layers, respectively. The fourth metal-wiring layer 17-4 forms an electrode pad 23. Also, reference numerals 13-1, 13-2, 13-3, and 13-4 denote a BPSG (boro-phospho silicate glass) film, a first interlayer insulation film, a second interlayer insulation film, and a third interlayer insulation film, respectively. A final protection film 19 is formed on the third interlayer insulation film 13-4. The final protection film 19 includes a pad opening 21 arranged over the electrode pad 23. The interlayer insulation films 13-2, 13-3, and 13-4 are provided with through holes 15-2, 15-3, and 15-4, respectively, to connect the metal-wiring layers adjacent above and below.
Since the electrode pad 23 is commonly formed by using the fourth metal-wiring layer 17-4, i.e., an uppermost metal-wiring layer, a structure of FIG. 2B having none of the first, second, and third metal-wiring layers 17-1, 17-2, and 17-3 may not have any problem in operations. Also, similarly, a structure of FIG. 2C having none of the through holes 15-2, 15-3, and 15-4 may not have any problem in operations.
One example of the related-art semiconductor apparatus has a device, such as a diode for protecting an input signal, arranged under the electrode pad. In this example, a plurality of diodes are disposed apart from each other at four locations corresponding to four corners of the electrode pad in order to avoid a direct transmission of an external impact to the diodes when the electrode pad is contacted by a bonding wire and the like.
FIGS. 3A-3C demonstrate a wafer test. FIG. 3A is a top view of a semiconductor 25. FIG. 3B is a cross-section side view in which a metal test probe 27 approaches a surface of the electrode pad 23. FIG. 3C is a cross-sectional side view in which the metal test probe 27 touches the electrode pad 23 and pushes the electrode pad 23 downwardly. At this time, the metal test probe 27 is pushes the electrode pad 23 by approximately 50 μm to approximately 100 μm. The test is conducted from one electrode pad to another in an efficient manner, i.e., at an extremely high speed, and therefore the contact of the metal test probe 27 to the surface of the electrode pad 23 is likely a high speed collision. An impact of such a collision may be transmitted through the structure and may cause a crack in the interlayer insulation film, for example.
FIG. 4 is a microphotograph showing a cross section of an evaluation sample of the above related-art semiconductor apparatus in a state after the metal test probe contacts the surface of the electrode pad. This evaluation sample has the four-metal-wiring-layer structure, similar to the structure shown in FIG. 2A. In this microphotograph, cracks 29 are seen in the third interlayer insulation film 13-4 under the electrode pad 23. The cracks 29 are made by the impact given by the metal test probe during the wafer test.
Some related-art semiconductor apparatuses integrate a driver transistor which is defined as a transistor having a relatively large channel width so as to drive a following device.
Operation of the driver transistor is explained with reference to a charging circuit used for a mobile cellular phone, for example, of FIGS. 5A and 5B. A charge battery 31 is connected to a power source 35 (e.g., a household AC wall outlet) via a charge switch 33. FIG. 5A shows the circuit in a state before the charging is conducted, that is, a transistor 37 is in an off state. To conduct charging, the transistor 37 needs to he turned on, so that the charge switch 33 connected to the transistor 37 via an electrode pad 23 is turned on. As a consequence, a current A (see FIG. 5B) flows from the power source 35 to the charge battery 31, and a charging to the charge battery 31 is performed.
In this circuit, the transistor 37 constitutes a driver transistor. In other words, the transistor 37 drives the following device, that is, the charge switch 33. Since the charging time can be reduced with an increase of the current A flowing through the transistor 37, a current B (see FIG. 5B) flowing through the transistor 37 which drives the transistor 37 also needs to be greater. Accordingly, the driver transistor needs to have a channel of a relatively greater width.
Referring to FIGS. 6A-6C, an exemplary layout of the driver transistor is explained. FIG. 6A is a top view of a typical driver transistor. FIG. 6B is a schematic top view. FIG. 6C is a cross-sectional side view taken in an A-A line of FIG. 6B.
As illustrated in FIG. 6C, a LOCOS (local oxidation of silicon) oxide film 3 is formed on a silicon substrate 1 to delimit a formation region 5 for forming a driver transistor therein. A source 7s and a drain 7d of an N-type impurity diffusion layer are formed in the formation region 5 of the silicon substrate 1. The source 7s and the drain 7d are arranged in parallel and alternately with a distance.
A gate electrode 11 of polysilicon is formed between the source 7s and the drain 7d on the silicon substrate 1 via a gate oxide film 9. FIGS. 6B and 6C show only four lines of the gate electrode 11; however, over several tens of the gate electrode is generally formed.
Although it is not shown, an interlayer insulation film 13 is formed on an entire surface of the silicon substrate 1, including formation areas of the source 7s, the drain 7d, and the gate electrode 11. A contact hole 15s is formed in the interlayer insulation film 13 provided on the source 7s, and a contact hole 15d is formed in the interlayer insulation film 13 provided on the drain 7d. Another contact hole is formed in the interlayer insulation film 13 provided on the gate electrode 11 in a region which is not shown.
A metal-wiring layer 17s is formed in a comb-like shape on the surface of the interlayer insulation film 13, including the formation region 5 of the contact hole 15s provided on the source 7s. A plurality of sources 7s are electrically connected to each other via the contact holes 15s and the metal-wiring layer 17s. The metal-wiring layer 17s is electrically connected to the electrode pad 23s formed on an electrode pad formation region of the interlayer insulation film 13 arranged in a vicinity to a driver transistor formation region.
Similarly, a metal-wiring layer 17d is formed in a comb-like shape on the surface of the interlayer insulation film 13, including the formation region 5 of the contact hole 15d provided on the drain 7d. A plurality of drains 7d are electrically connected to each other via the contact holes 15d and the metal-wiring layer 17d. The metal-wiring layer 17d is electrically connected to the electrode pad 23d formed on an electrode pad formation region of the interlayer insulation film 13 arranged in a vicinity to a driver transistor formation region.
In a region not shown, a metal-wiring layer is formed on a region including a formation region of the contact hole provided on the gate electrode 11. A plurality of gate electrodes 11 are electrically connected to each other via the contact holes and the metal-wiring layers which are not shown.
A final protection film 19 is formed on the interlayer insulation film 13. The final protection film 19 includes pad openings 21s and 21d on the electrode pad 23s and the electrode pad 23d, respectively.
As illustrated in FIG. 6C, an alternate arrangement of the sources 7s and the drains 7d is one of typical characteristics of the driver transistor. A current flows in directions, as indicated in FIG. 6C. That is, each of the source 7s and the drain 7d acts on the gate electrodes 11 adjacent thereto on both sides. Accordingly, this structure has an advantage to allow a relatively great current flow with a relatively small area.
FIGS. 7A-7C, 8A, 8B, and 9A and 9B illustrate another related-art semiconductor apparatus having a four-metal-wiring-layer structure. FIG. 7A is a top view of the related-art semiconductor apparatus. FIG. 7B is a cross-sectional side view taken in an A-A line of FIG. 7A, and FIG. 7C is a cross-sectional side view in a B-B line of FIG. 7A. FIG. 8A is a top view of a first metal-wiring layer, and FIG. 8B is a top view of a second metal-wiring layer. FIG. 9A is a top view of a third metal-wiring layer, and FIG. 9B is a top view of a fourth metal-wiring layer.
A LOCOS (local oxidation of silicon) oxide film 3 is formed on the silicon substrate 1. The sources 7s and the drains 7d are arranged alternately with a distance in the formation region of the driver transistor on the silicon substrate 1.
The gate electrode 11 of polysilicon is formed between the source 7s and the drain 7s on the silicon substrate 1 via the gate oxide film 9.
The BPSG film 13-1 is formed on the entire surface of the silicon substrate 1, including the formation regions of the source 7s, the drain 7d, and the gate electrode 11. A contact hole 15s-1 is formed in the BPSG film 13-1 on the source 7s, and a contact hole 15d-1 is formed in the BPSG film 13-1 on the drain 7d. Also, in a region not shown, a contact hole is formed in the interlayer insulation film 13 on the gate electrode 11.
A first metal-wiring layer 17s-1 is formed on a surface of the BPSG film 13-1, including a formation region of the contact hole 15s-1 provided on the source 7s. A first metal-wiring layer 17d-1 is formed on a surface of the BPSG film 13-1, including a formation region of the contact hole 15d-1 provided on the source 7d. Also, in a region not shown, a metal-wiring layer is formed on a surface of the BPSG film 13-1, including a formation region of the contact hole provided on the gate electrode 11.
A first interlayer insulation film 13-2 is formed on a surface of the BPSG film 13-1, including formation regions of the first and second metal-wiring layers 17s-1 and 17d-1. A through hole 15s-2 is formed in the first interlayer insulation film 13-2 created on the first metal-wiring layer 17s-1. A through hole 15d-2 is formed in the first interlayer insulation film 13-2 created on the first metal-wiring layer 17d-1.
A second metal-wiring layer 17s-2 is formed on a surface of the first interlayer insulation film 13-2, including a formation region of the through hole 15s-2 provided on the first metal-wiring layer 17s-1. Also, a second metal-wiring layer 17d-2 is formed on a surface of the first interlayer insulation film 13-2, including a formation region of the through hole 15d-2 provided on the first metal-wiring layer 17d-1.
A second interlayer insulation film 13-3 is formed on a surface of the first interlayer insulation film 13-2, including formation regions of the second metal-wiring layers 17s-2 and 17d-2. A through hole 15s-3 is formed in the second interlayer insulation film 13-3 provided on the second metal-wiring layer 17s-2, and a through hole 15d-3 is formed in the second interlayer insulation film 13-3 provided on the second metal-wiring layer 17d-2.
A third metal-wiring layer 17s-3 is formed on a surface of the second interlayer insulation film 13-3, including a formation region of the through hole 15s-3 formed on the second metal-wiring layer 17s-2. A third metal-wiring layer 17d-3 is formed on a surface of the second interlayer insulation film 13-3, including a formation region of the through hole 15d-3 formed on the second metal-wiring layer 17d-2.
A third interlayer insulation film 13-4 is formed on a surface of the second interlayer insulation film 13-3, including formation regions of the third metal-wiring layers 17s-3 and 17d-3. A through hole 15s-4 is formed in the third interlayer insulation film 13-4 provided on the third metal-wiring layer 17s-3, and a through hole 15d-4 is formed in the third interlayer insulation film 13-4 provided on the third metal-wiring layer 17d-3.
A fourth metal-wiring layer 17s-4 is formed on a surface of the third interlayer insulation film 13-4, including a formation region of the through hole 15s-4 provided on the third metal-wiring layer 17s-3. The fourth metal-wiring layer 17d-4 covers formation regions of a driver transistor and an electrode pad. The fourth metal-wiring layer 17s-4 covers formation regions of a plurality of the third metal-wiring layers 17s-3, and is electrically connected to the plurality of the third metal-wiring layers 17s-3 via a plurality of the through holes 15s-4.
A fourth metal-wiring layer 17d-4 is formed on a surface of the third interlayer insulation film 13-4, including a formation region of the through hole 15d-4 provided on the third metal-wiring layer 17d-3. The fourth metal-wiring layer 17d-4 covers formation regions of a driver transistor and an electrode pad in a region where the fourth metal-wiring layer 17s-4 is not formed. The fourth metal-wiring layer 17d-4 covers formation regions of a plurality of the third metal-wiring layers 17d-3, and is electrically connected to the plurality of the third metal-wiring layers 17d-3 via a plurality of the through holes 15d-4.
A final protection film 19 is formed on a surface of the third interlayer insulation film 13-4, including formation regions of the fourth metal-wiring layers 17s-4 and 17d-4. A pad opening 21s is formed in the final protection film 19 provided on the fourth metal-wiring layer 17s-4 in a formation region of the electrode pad, and a pad opening 21d is formed in the final protection film 19 provided on the fourth metal-wiring layer 17d-4 in a formation region of the electrode pad. The fourth metal-wiring layers 17s-4 and 17d-4 under formation regions of the pad openings 21s and 21d form electrode pads 23s and 23d, respectively.
The electrode pad 23s is electrically connected to the source 7s via the fourth metal-wiring layer 17s-4, the through hole 15s-4, the third metal-wiring layer 17s-3, the through hole 15s-3, the second metal-wiring layer 17s-2, the through hole 15s-2, the first metal-wiring layer 17s-1, and the contact hole 15s-1.
The electrode pad 23d is electrically connected to the drain 7d via the fourth metal-wiring layer 17d-4, the through hole 15d-4, the third metal-wiring layer 17d-3, the through hole 15d-3, the second metal-wiring layer 17d-2, the through hole 15d-2, the first metal-wiring layer 17d-1, and the contact hole 15d-1.
The electrode pad 23d is electrically connected to the drain 7d vie the fourth metal-wiring layer 17d-4, the through hole 15d-4, the third metal-wiring layer 17d-3, the through hole 15d-3, the second metal-wiring layer 17d-2, the through hole 15d-2, the first metal-wiring layer 17d-1, and the contact hole 15d-1.
In this way as described above, a plurality of metal-wiring layers are formed one on another in a multi-layered form and have connections with a plurality of through holes and a contact hole. A reason for this is that it is advantageous if a resistance element in a current path at the channels of source 7s and drain 7d can be reduced as small as possible since the driver transistor aims to allow a large amount of current flow.
The first metal-wiring layers 17s-1 and 17d-1, the second metal-wiring layers 17a-2 and 17d-2, and the third metal-wiring layers 17s-3 and 17d-3 form a pattern in a linear shape. However, the fourth metal-wiring layers 17s-4 and 17d-4 form a pattern of a large rectangle shape. This is because the fourth metal-wiring layers need to be thick to allow a large amount of current flow since the currents flowing through the first, second, and third metal-wiring layers enter together into the fourth metal-wiring layers.
The fourth metal-wiring layers 17s-4 and 17d-4 are formed across the metal-wiring layers 17s-1, 17s-2, and 17s-3 in the source side and the metal-wiring layers 17d-1, 17d-2, and 17d-3 in the drain side. Therefore, no through hole is formed on the third metal-wiring layer 17d-3 in the drain side under the fourth metal-wiring layer 17s-4 in the source side. Similarly, no through hole is formed on the third metal-wiring layer 17s-3 in the source side under the fourth metal-wiring layer 17d-4 in the drain side.
The above-described related-art semiconductor apparatus having the driver transistor under the electrode pad may cause such a problem as explained below with reference to FIGS. 10A-10C. FIG. 10A is a top view of the related-art semiconductor apparatus. FIG. 10B is a cross-sectional side view taken in an A-A line of FIG. 10A, and FIG. 10C is a cross-sectional side view taken in a B-B line of FIG. 10A.
In this apparatus, the electrode pads 23s and 23d are formed over the driver transistors. As described above, the third interlayer insulation film 13-4 provided under the electrode pads 23s and 23d may have the cracks 29 due to an impact caused by a collision of the electrode pad with a metal test probe during a wafer test. The cracks 29 can make an electrical short circuit between the fourth metal-wiring layers 17s-4 and 17d-4 and the third metal-wiring layers 17s-3 and 17d-3.
Due to the cracks 29, the fourth metal-wiring layer 17d-4 in the drain side and the third metal-wiring layer 17s-3 in the source side are short-circuited, and the fourth metal-wiring layer 17s-4 in the source side and the third metal-wiring layer 17d-3 in the drain side are short-circuited. In this situation, the driver transistors cannot properly operate.
The above-described problem is caused not only in a case where a device arranged under an electrode pad is a driver transistor but also in a case where a device has two electrodes which are drawn to and connected to the two electrode pads in a way such that a metal-wiring layer electrically connected to one of the two electrodes is arranged under an electrode pad electrically connected to the other one of the two electrodes.